TMDS (Transition Minimized Differential Signaling) is a technology for transmitting high-speed serial data and is used by video interfaces, such as HDMI (High-Definition Multimedia Interface) and DVI (Digital Visual Interface).
In a receiver (Rx) with Transition Minimized Differential Signaling (TMDS) standards or High Definition Multimedia interface (HDMI) standards, a clock channel (e.g. channel C) for transmitting a clock signal and three color channels (e.g. channel [0:2]) for transmitting serial data of R, G, and B are usually adopted.
In accordance with TMDS standards and HDMI standards, the clock signal is 25˜165 MHz while a data rate of the color channels is ten times the clock signal. That is, the color channel transmits a serial data with 10 bits during a clock cycle, and the receiver with TMDS standards or HDMI standards must recovery the serial data with 10 bits in the color channels respectively.
In order to improve the success rate of data recovery, an over-sampling data recovery method is typically adopted. For example, in U.S. Pat. No. 5,905,769 titled “System and method for high-speed skew-insensitive multi-channel data transmission”, a 3× over-sampling data recovery method and system is disclosed.
Please refer to FIG. 1. FIG. 1 is a diagram illustrating a conventional 3× over-sampling data recovery system according to prior art. The data recovery system consists of a charge pump phase locked loop (PLL) 20, an over-sampler 26, and a digital PLL 30. The digital PLL 30 further includes a phase-aligning window 50, a detection logic circuit 52, a digital loop filter 54, and a phase-aligning finite state machine (FSM) 56. In addition, the charge pump PLL 20 receives a clock signal (CLK) 22, and the over-sampler 26 receives a serial data 28, e.g. any one serial data of the three color channels.
Furthermore, the charge pump PLL 20 receives the clock signal 22, and then generates twelve multiplicative clock signals 24 with a phase difference of 30 degrees to the over-sampler 26 by performing a 2.5× frequency multiplication on the clock signal 22. The over-sampler 26 samples the serial data 28 according to the multiplicative clock signals 24, so as to generate fourteen over-sampled data, i.e. the 14-bit data, to the phase-aligning window 50. The phase-aligning window 50 selects twelve over-sampled data from the 14-bit data as a 12-bit signal 62 and then selects four designated bits from the 12-bit signal 62 as a 4-bit signal 64 to be outputted. After that, the detection logic circuit 52 generates two phase detection signals, i.e. a phase-up signal (UPF) 66 and a phase-down signal (DOWNF) 68, to the digital loop filter 54 according to the 12-bit signal 62. The digital loop filter 54 then generates three phase correction recommendation signals, i.e. an UP signal (UPT) 70, a hold signal (HOLD) 72, and a down signal (DOWNT) 74, to phase-aligning FSM 56 according to the received phase-up signal 66 and the phase-down signal 68. Finally, the phase-aligning FSM 56 generates a phase selection signal 58 to the phase-aligning window 50 according to the up signal 70, the hold signal 72, and the down signal 74, and thereby the phase-aligning window 50 selects twelve over-sampled data from the 14-bit data as the 12-bit signal 62 and selects four designated bits from the 12-bit signal 62 as the 4-bit signal 64 to be outputted.
Please refer to FIG. 2A. FIG. 2A is a diagram illustrating 3× over-sampling data recovery according to prior art. The charge pump PLL 20 generates twelve multiplicative clock signals 24-1˜24-12 with a phase difference of 30 degrees by performing a 2.5× frequency multiplication on the clock signal 22. Due to the serial data 28 having 10 bits 28-1˜28-10 during a clock cycle, each bit of the ten bits can be sampled for three times by sequentially sampling the ten bits based on the rising-edges of the twelve multiplicative clock signals 24.
Please refer to FIG. 2B. FIG. 2B is a diagram illustrating 3× over-sampling data recovery according to prior art. When a 4-bit data is sequentially sampled based on the rising-edges of the twelve multiplicative clock signals 24, an over-sampled data with 12 bits, i.e. S[0], S[1] . . . , S[11], can be generated. Therefore, a 14-bit signal can be obtained by adding the over-sampled data with 12 bits, a latest over-sampled bit S′[11] of the previous over-sampled data, and a first over-sampled bit S″[0] of the next over-sampled data up.
For example, assume that the four bits 28-1, 28-2, 28-3, and 28-4 of the serial data 28 are 1, 0, 1, and 0. The first bit 28-1 is sequentially sampled according to the rising edges of the multiplicative clock signals 24-1, 24-2, and 24-3, wherefore S[0]=S[1]=S[2]=1. The second bit 28-2 is sequentially sampled according to the rising edges of the multiplicative clock signals 24-4, 24-5, and 24-6, wherefore S[3]=S[4]=S[5]=0. The third bit 28-3 is sequentially sampled according to the rising edges of the multiplicative clock signals 24-7, 24-8, and 24-9, wherefore S[6]=S[7]=S[8]=1. The fourth bit 28-4 is sequentially sampled according to the rising edges of the multiplicative clock signals 24-10, 24-11, and 24-12, wherefore S[9]=S[10]=S[11]=0. In other words, the serial data 28 and the multiplicative clock signals 24 are under a perfect synchronization. The 12-bit signal consists of S[0]˜S[11], wherein S[0], S[4], S[7], and S[10] are selected from the 12-bit signal as the 4-bit signal. Accordingly, the four bits 28-1, 28-2, 28-3, and 28-4 of the serial data 28 are successfully recovered to their correct logic values, i.e. S[1]=1, S[4]=0, S[7]=1, and S[10]=0.
On the other hand, the detection logic circuit 52 uses three sampled data as a unit, and determines whether to output the phase-up signal (UPF) 66 or the phase-down signal (DOWNF) 68 according to the logic values of the 12-bit signal S[0]˜S[11]. Since S[0]=S[1]=S[2]=1, S[3]=S[4]=S[5]=0, S[6]=S[7]=S[8]=1, and S[9]=S[10]=S[11]=0 under a perfect synchronization, the phase-up signal (UPF) 66 or the phase-down signal (DOWNF) 68 won't be outputted by the detection logic circuit 52. As a result, the hold signal (HOLD) 72 is received by the phase-aligning FSM 56, and the phase selection signal 58 notifies the phase-aligning window 50 to maintain the present phase selection.
Please refer to FIG. 2C. If the serial data 28 and the multiplicative clock signals 24 are under an imperfect synchronization, the 14-bit signal is listed below: S′[11]=1, S[0]=1, S[1]=1, S[2]=0, S[3]=0, S[4]=0, S[5]=1, S[6]=1, S[7]=1, S[8]=0, S[9]=0, S[10]=0, S[11]=1, and S″[0]=1. At this time the 12-bit signal consists of S[0]˜S[11], wherein S[1], S[4], S[7], and S[10] are selected from the 12-bit signal as the 4-bit signal. The four bits 28-1, 28-2, 28-3, and 28-4 of the serial data 28 can be successfully recovered to their correct logic values, i.e. S[1]=1, S[4]=0, S[7]=1, and S[10]=0. However, due to S[0]=S[1]≠S[2], S[3]=S[4]≠S[5], S[6]=S[7]≠S[8], and S[9]=S[10]≠S[11], the detection logic circuit 52 outputs the phase-up signal (UPF) 66. As a result, the up signal (UPT) 70 is received by the phase-aligning FSM 56, and the phase selection signal 58 notifies the phase-aligning window 50 to change the phase selection, which makes the 12-bit signal consist of S′[11], S[0], S[1], S[2], S[3], S[4], S[5], S[6], S[7], S[8], S[9], and S[10]. Accordingly, S′[11]=S[0]=S[1], S[2]=S[3]=S[4], S[5]=S[6]=S[7], and S[8]=S[9]=S[10], which returns to the perfect synchronization again.
Generally speaking, the conventional over-sampling data recovery method and system usually adopts an odd over-sampling method and system, e.g. a 3× over-sampling method/system or a 5× over-sampling method/system, wherein such approaches must utilize a charge pump PLL with a frequency multiplication over 2.5 times. In addition, the abovementioned two methods/systems can only sample a serial data with 4 bits each time. Take the 3× over-sampling method/system for example, errors might be caused in the sampled data when the serial data skews too seriously, which results in a condition that the data cannot be correctly recovered.